Fractile's $720M Round Bets on Stacked DRAM to Break the AI Memory Bottleneck

The headline number is the $720 million, but the more interesting detail is the engineering bet behind it. Fractile, a British startup building AI inference chips, says its processors can deliver up to 100 times the performance of current silicon while cutting energy use by 90%. Those are company projections, and the chips won't ship until next year. Still, they target a specific bottleneck, and the way Fractile plans to attack it is worth a close look.

Where the time actually goes

A large language model doesn't produce a response in one pass. It works through a sequence of processing steps, and at the end of each one, the intermediate results get written out to off-chip HBM memory. Before the next step can begin, those results have to be fetched back. Each of those round trips costs time and energy, and across a long chain of steps, the cost adds up. Here's the thing: the arithmetic units on a modern accelerator are often not the limiting factor. Moving data to and from memory is.

That's why so much recent hardware work has focused on the distance between compute and memory rather than on raw compute alone. Shorten the path, and you reduce both latency and the power spent shuttling bits back and forth.

Two different ways to shorten the trip

Cerebras Systems, which went public in May, takes one route. Its wafer-scale accelerators keep working data in a large onboard cache built from SRAM. That cache is faster than off-chip HBM, and the company's newest processor, the WSE-3T, holds 44 gigabytes. The tradeoff is that SRAM is expensive and hard to scale in capacity. Each SRAM cell uses six transistors, which is why it's fast, and also why it's costly to pack in large amounts. Historically, SRAM showed up on processors in modest quantities, not in the tens of gigabytes.

Fractile is skipping SRAM entirely. Instead, it plans to stack standard DRAM on top of its inference logic. Placing a memory layer directly above the logic circuits means data has only a very short vertical distance to travel. DRAM is denser and cheaper per bit than SRAM, so the approach trades some of SRAM's raw speed for far more capacity, and it does so using a memory technology the industry already knows how to manufacture at volume. My read is that this is the more interesting bet for deployment economics, because it hinges on whether 3D stacking can deliver bandwidth and latency good enough to matter, not on whether on-chip memory is fast in isolation.

Memory vendors are chasing the same problem

Samsung Electronics is working on a related idea. In August, it introduced an HBM variant called zHBM that can be stacked atop AI accelerators and uses tiny copper wires to move data to and from the host chip. Samsung says zHBM will be eight times faster than HBM5, a future generation of HBM that it describes as more capable than today's versions. Those figures come from Samsung and haven't been independently verified, but the direction is clear. Memory makers see data movement as the constraint worth redesigning around, and so do chip startups. When both camps converge on the same problem from different sides, it usually means the bottleneck is real and durable.

What Fractile is actually selling

Fractile estimates its chips will let an LLM process several thousand tokens per second. It doesn't plan to sell bare silicon. The processors will ship as part of rack-scale systems that include custom software. That matters, because hardware performance on paper only translates to production value if the software stack maps real models onto the silicon efficiently. Many AI chipmakers rely on compilers that automatically convert a customer's model into a format their hardware can execute. Buyers evaluating a platform like this will want to know how broad that model support is, how much tuning a new architecture demands, and how the rack-level systems fit into existing data center designs.

Those questions are where the gap between a projection and a deployed system tends to show up. A 100x claim measured on a favored workload can look very different across a diverse model mix, and energy figures depend heavily on the operating point and the system around the chip.

Backers and valuation

The round was led by Thrive Capital, Founders Fund, Lightspeed and Redpoint, and about a dozen other investors joined, including CapitalG, the investment arm of Alphabet Inc., the U.K. Sovereign AI Fund and the British Business Bank. The round puts Fractile's valuation at $7 billion. Fractile was founded in 2022 by AI researcher Walter Goodwin, who serves as chief executive. The company's pitch rests on an architectural argument rather than a long shipping record, so the valuation signals investor conviction in that architecture more than proven revenue.

The next thing to watch is the first shipments. Independent measurements against well-known models, the maturity of the compiler and runtime, and how stacked DRAM holds up thermally and in yield at production scale will tell us far more than the headline multiples. If the numbers hold, Fractile's approach could make the memory layout of inference hardware a central design question again.