AMD's Venice-X Returns 3D V-Cache to EPYC at a 5.3 GHz Boost Clock

AMD's stacked-cache line went quiet in the data center for a while. Turin never got an X variant, so the gap ran from Genoa-X in 2023 to now. Venice-X closes that gap, and it does so with a different emphasis than its predecessors. The headline spec isn't a bigger cache or more cores. It's frequency.

Why the boost clock matters more than the cache this time

Venice-X keeps the numbers that define the Genoa-X part: 96 cores, 192 threads and 1,152 MB of L3. Where it departs is the boost clock, which reaches 5.3 GHz. That's the top of the Venice range, and it's a big jump over the EPYC 9684X's 3.7 GHz boost.

That matters because of how the earlier X chips were positioned. Milan-X and Genoa-X traded frequency for cache. The standard Milan parts scaled to 4.1 GHz and Genoa to 4.4 GHz, but the X variants stayed well below those ceilings. Anyone who wanted high clocks bought the standard chips, and anyone who needed a large cache bought the X chips. Venice-X is meant to remove that choice for HPC buyers, with the stacked cache and the highest frequency on the same package.

Here's the spec comparison as far as AMD has disclosed it:

Several gaps remain. AMD hasn't disclosed the base clock, the number of Venice-X SKUs or their individual specs. The TDP is also unconfirmed, though the 400 to 600 W range that other Venice CPUs use is the reasonable working assumption. The chips appear to use the SP7 socket, which matches how earlier EPYC -X parts were deployed.

Platform and memory

On SP7, Venice-X gets the full 16-channel memory layout and 96 PCIe 6.0 lanes. The smaller SP8 socket, aimed at enterprise deployments, gives up memory channels to get more PCIe lanes. Venice-X doesn't take that trade. It supports MRDIMMs at 12,800 MT/s, and AMD quotes 1.6 TB/s of per-socket memory bandwidth. That's close to four times what the Genoa-X generation offers per socket, according to AMD's figures.

For HPC codes that stream large working sets, bandwidth and cache both count. Stacked L3 keeps hot data on-package, and wide memory keeps the cores fed when the working set spills out of cache. Pairing them with 5.3 GHz clocks is aimed squarely at workloads that are sensitive to both.

What AMD runs internally

The clearest view into Venice-X's purpose comes from how AMD uses its own fleet. The company runs both 3D V-Cache and high-frequency EPYC chips for internal electronic design automation (EDA) work. Fellow Phil Steinke says AMD profiles these workloads to characterize performance, guide EPYC design decisions and push software vendors to optimize their code.

The largest consumer is function verification, which accounts for more than half of AMD's used compute, according to Steinke. These are logic simulations run in tools such as Cadence Xcelium, and Steinke says the team runs them "24 x 7 x 365."

AMD's chart tracks IPC using its uProf monitoring utility. In the comparison, the workload with 3D V-Cache finishes about 40% faster, at roughly double the instructions per clock. AMD hasn't said which chips were compared or which application was used. The comparison is between an EPYC fleet with 3D V-Cache and one without it, so treat the figures as directional until the test setup is public.

Steinke's argument is that the split between cache-heavy and frequency-heavy machines was always a compromise. "I mentioned we have a mix of high frequency and 3D V-Cache CPUs in our data center, and that's because through Milan and Genoa, the high frequency parts were always a little higher on the frequency side," he said. "You don't have that dichotomy [with Venice-X]. You can get the best of both worlds in a single CPU, and this is what we're really excited to be picking up for our own use."

Where the frequency parts already stand

AMD hasn't published Venice-X benchmarks yet. It has, however, compared its high-frequency EPYC 9686F against Intel's Xeon 6980P on several HPC workloads, including computational fluid dynamics. In AMD's testing, the 9686F was 1.6x faster while running 32 fewer cores. Those are vendor numbers, and they describe the high-frequency part, not Venice-X.

We ran some of our own tests on the 9686F alongside the denser EPYC 9996, and the 9686F held up well on several HPC workloads. The clearest exception was CloverLeaf, a hydrodynamics code that's sensitive to memory latency. Our testbed was a 2P configuration, and the only Xeon 6980P we had was a single socket, so the comparison isn't apples to apples. Even so, the 2P EPYC 9686F finished the simulation in about a third of the time the single Xeon took.

Memory capacity and what comes next

AMD is also leaning on MEXT, its AI-driven flash-as-DRAM technology, to expand the memory available to its EDA workloads. Steinke says that will continue once Venice-X is in the fleet. Memory capacity is a practical limit for verification farms, so a tiering approach like this can matter as much as raw cache size. You can read more about MEXT in our separate breakdown.

Timing is the other piece. SP7 and SP8 Venice CPUs are shipping now, while Venice-X arrives in the second half of 2027. AMD is also positioning Verano for the second half of 2027 as an AI host node built around SOCAMM2 LPDDR5X memory.

My read: the interesting question isn't whether Venice-X can hit 5.3 GHz. It's whether the single-socket promise holds up. If the final SKUs deliver high clocks and 1,152 MB of cache without the frequency penalty that defined Milan-X and Genoa-X, AMD will have answered a split that has pushed HPC operators into maintaining two fleets. Base clocks, TDP and actual SKU lineup will decide how much of that holds in practice, and those numbers are still missing.